The present invention is related to correlated double sampling circuits.
A charge-coupled device (CCD) output waveform is a sequence of pixels, where each pixel is represented as the difference between a reset level and a data level. This signal waveform is initially processed before being passed on to the automatic gain control (AGC) circuit:
The data level is subtracted from the reset level on a pixel-by-pixel basis to remove the reset noise component common to both signals. This operation is called correlated double-sampling (CDS).
One prior art CDS is shown in block diagram form in FIG. 1(a) with an associated control signal timing diagram shown in FIG. 1(b). FIG. 1(a) shows a pipelined CDS circuit. The circuit has two non-overlapping time phases of operation: In the Q1 phase of the pipelined CDS circuit, the reset level is sampled by sample-and-hold (S/H) #1. A schematic diagram of a typical S/H is shown in FIG. 2. In the Q2 phase, the data level is sampled by S/H #2. Simultaneously, S/H #3 samples the output of S/H #1.
Drawbacks of the pipelined CDS technique are: (1) There are three sampling operations, which increases the noise over techniques requiring only two sampling operations; and (2) Any gain or offset mismatch between the reset path (S/H #1 and S/H #3) and the data path (S/H #2) limits the ability of the CDS to remove reset noise.
Another prior art CDS is shown in FIG. 3(a). The associated timing diagram is shown in FIG. 3(b). FIG. 3(a) shows a dual CDS circuit.
S/H #1 and S/H #2 form a single CDS circuit, and S/H #3 and S/H #4 form a second single CDS circuit. Each single CDS processes alternate pixels. Thus, two CDS circuits are required to process all pixels.
The dual CDS has four phases of operation: In the Q1A phase, the reset level of the first pixel is sampled by S/H #1. The output switch is set to B. In the Q1B phase, the data level of the first pixel is sampled by S/H #2. The output switch is set to B. In the Q2A phase, the reset level of the second pixel is sampled by S/H #3. The output switch is set to A. In the Q2B phase, the data level of the second pixel is sampled by S/H #4. The output switch is set to A.
Compared to the pipeline CDS of FIG. 1(a), the dual CDS has lower noise because only two sampling operations are performed for each pixel. Also, the AGC has a fall period to sample each pixel.
Drawbacks of the dual CDS scheme include: (1) Two CDS circuits are required because the previous pixel value must be held while the reset level of the next pixel is sampled; and (2) Even and odd pixels use different CDS circuits, causing gain and offset errors which must be removed.
Applicants herein have discovered that in both prior art techniques, it is difficult to apply a variable gain within the CDS.
The present invention is directed to a correlated double sampling circuit which is able to remove correlated noise and sample each pixel with no internal offset.
One embodiment of the invention is directed to an amplifier circuit including an amplifier having an input and an output. The circuit also includes an input terminal that receives an input signal. An input capacitor is coupled between the input of the amplifier and the input terminal, onto which input capacitor charge from the input signal is sampled during a first of first and second time phases. A feedback capacitor, coupled between the input and the output of the amplifier, receives charge from the input capacitor during the second time phase. No sampling switch is located between the input capacitor and the input terminal.
In an embodiment, the input capacitor includes a variable capacitor.
In an embodiment, the feedback capacitor includes a variable capacitor.